RTL Design Engineer
How has GenerativeAI changed the way data center infrastructure is built and scaled? How can a new interconnect architecture reduce bottlenecks in hyper-distributed systems? If you're passionate about building ground-breaking products to connect and move data across AI infrastructure, this opportunity might be for you!
Acceler8 Talent is seeking an experienced RTL Design Engineer to join a mature startup in the Bay Area. As a member of this highly accomplished team, you would collaborate with world-class distributed systems hardware and software architects to transform product visions for industry-leading GPU computing networks.
In order to solve the critical bottleneck in next-generation computing workloads, this company is seeking highly motivated and talented engineers who are excited to grow in a fast-paced startup environment. As an RTL Design Engineer, you would own all aspects of the logic design process and deliver a robust, high-performance design that meets all cross-functional engineering requirements. You would support functional verification, performance validation, and silicon bringup and post-silicon testing.
This role might be ideal for you if you have:
- Proven industry experience with high-performance packet buffering subsystems (knowledge of traffic management concepts)
- Successful track records in designing high-performance Network Interface Controllers, Smart-NICs, or DPUs processing pipelines (capability in designing blocks like DMA controllers)
- Expert knowledge of SystemVerilog and knowledge of Perl/Python/other scripting languages
- BSEE/CE or MSEE/CE + professional experience in a relevant industry
This is a hybrid/remote position based in the Bay Area.
Base salary: $230,000
